About the role#
Join the ASIC team as a Design Verification Intern. You will work on high-performance compute and networking standards in advanced CMOS process nodes. This role focuses on the design and verification of blocks using modern methodology and tools.
What you'll do#
- Design and verify blocks using industry tools.
- Collaborate with the ASIC team on hardware projects.
- Engage in work related to digital logic and computer architecture.
- Write scripts using Python or Perl to support verification tasks.
What you'll need#
- Completed 3rd year of study toward a degree in Computer Engineering or Electrical/Electronic Engineering.
- Minimum GPA of 3.5.
- Hands-on knowledge of RTL design languages and tools, specifically Verilog and System Verilog.
- Experience with C/C++.
- Authorization to work in Canada.
- Strong analytical and debugging skills.
- Familiarity with high-speed interfaces like PCIe, DDR, or HBM is a plus.
Location & details#
- Location: Toronto, Ontario, Canada.
- Work modality: On-site.
- Term: Summer 2026.
- Status: Full-time and paid internship.
About Astera Labs
Astera Labs is a semiconductor company based in San Jose, California. Founded in 2017, the firm develops connectivity solutions for rack-scale AI infrastructure. It serves hyperscalers and ecosystem partners by integrating hardware technologies with its proprietary software suite. The company currently employs over 1,100 people across global office locations.
How to get in at Astera Labs
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